The present invention relates generally to digital receiver circuits and, more particularly, to an apparatus for hysteresis based process compensation for CMOS receiver circuits.
It is well known in the art to use CMOS (Complementary Metal Oxide Semiconductor) receivers to interface with input signals from off-chip, signals that typically operate at a different voltage with respect to the internal, on-chip devices. One common type of CMOS receiver is what is referred to as a NAND-INVERTER 100, shown in FIG. 1. This receiver 100 includes a first NAND gate stage 102 and a second inverter stage 104, and has a pair of inputs thereto. A first input (PAD) represents the actual data that is input to the receiver, while a second input (ENABLE) is used to selectively pass the input signal received at the data input (PAD). Otherwise, the output (OUT) of the receiver 100 is driven to logic 0 regardless of the value of the input signal.
As particularly shown in the insert portions of FIG. 1 (which depict the transistor arrangement of the NAND and inverter stages), the data input PAD is connected to the gates of PFET P1 and NFET N1. Similarly, the ENABLE input is connected to the gates of PFET P2 and NFET N2. The PFETs P1 and P2 are connected in parallel, while the NFETs N1 and N2 are connected in series, thereby forming a NAND gate 102 of conventional design. The output of the NAND gate 102 defines an intermediate node 106, which is connected to the gates of PFET P3 and NFET N3 (arranged as a conventional inverter 104), the output of which is the output of the receiver 100. For such an off-chip receiver, the input NAND stage 102 operates at the off-chip voltage (VDD2) while the output inverter stage 104 operates at the internal chip voltage (VDD).
Depending on process variations, among other things, the input voltage at which the output of a CMOS inverter switches can vary by as much as 700 or 800 mV. Due to this variation, the switch point of the CMOS inverter tends to be unstable and susceptible to noise. Consequently, the use of hysteresis effects enables suppression of output noise by adjusting the threshold voltages of the pull up and pull down devices in a CMOS receiver, depending on the present state of the output. For example, FIG. 1 further illustrates the use of hysteresis through a pair of inverter stages 108, 110, configured as a latch that reinforces the value of the intermediate node 106.
This arrangement is intended to create a higher input voltage threshold value (VTH) when the output transitions from low to high, and a lower input voltage threshold value (VTL) when the output transitions from high to low. Thereby, an input noise margin of VTH-VTL is provided.
However, as secondary input/output supply voltages have become lower and lower over time, the effects of PFET to NFET mistracking have become a larger percent of the total hysteresis range. This has, in turn, caused the hysteresis effects to approach or move outside of specifications under certain process conditions that have NFET to PFET skew. Accordingly, it would be desirable to be able to compensate for such devices that fall within design specifications but that do not produce acceptable yield results due to process skew.